AD9545 Evaluation Board (EVAL-AD9545) Survival Guide

The AD9545 is a great chip with quite unique features, including the 1PPS jitter-cleaning lock. If you dig deeper, you'll find that you need to provide your own TCXO/OCXO and use AuxDPLL for system clock compensation to manage that—but that's fine, we're seasoned, so it’s all right.

For your setup, you have the DPLL set for 50mHz loop bandwidth. For this low loop bandwidth, the XTAL for the system clock is not stable enough. This type of application will require a very stable TCXO or OCXO to use in conjunction with the system clock.

I would recommend applying a frequency source that is very stable over temperature and use the "AuxDPLL" for the system clock compensation. This can be done in the GUI software. You can send the signal to an unused reference input. For the AUXDPLL, the loop bandwidth can be set ~50Hz. Once that is locked, choose to apply the system clock compensation to DPLL0 and the TDCs. 

You'll also need to disregard the AD9545 Evaluation Board User Guide, which states:

By default, the AD9545 system clock input is configured to the on-board 49.152 or 50 MHz crystal

The crystal actually provided is 52MHz, as you can see if you flip the board around.

Additionally, you will need to purchase the SN65LVDS4EVM LVDS Receiver board, as the AD9545 Evaluation Board is wired with "LVDS-compatible outputs," which are quite difficult to use to drive any "regular" logic (at least by my definition of regular).

However, the final step to "win" this AD9545 game, no matter how hard you try to avoid it, will be... unsoldering components.

You definitely need to remove the R318 and R319 50-Ohm termination resistors. Analog Devices has gone the extra mile to make REF B/BB as "normal" as possible:

In contrast, REF B/BB (Connectors J302 and J303, respectively) are configured for single-ended CMOS inputs by default. Each reference input logic type is configurable via the evaluation software. REF B is intended for a DC-coupled, 1.8V/1.2V CMOS input and is terminated with only a 50Ω resistor to ground. REF BB is intended for a either a DC-coupled, 5V CMOS input, and the on board voltage divider will decrease the input amplitude to 1.8V, or a 3.3V CMOS input which will be reduced to a 1.2V CMOS signal.

At the last moment, they made a misstep by using those 50-Ohm resistors. Both inputs are 50-Ohm terminated. While I can drive these 50-Ohm terminated CMOS inputs with my signal generator, they completely disrupt signals coming from standard logic (like microprocessors). I understand that in the RF world or for extremely high-frequency clocks, 50-Ohm termination makes sense, but it doesn’t align with the 'CMOS input' claims in the documentation. And as for the voltage dividers mentioned? I don't see any on my board.

So, be cautious when driving REF B/BB. Maybe they're assuming a 50-Ohm source resistance, which would result in a 6 dB attenuation with the 50-Ohm termination, reducing 3.3V to 1.8V. But that's making too many assumptions for my liking. I removed those resistors, and now the inputs work fine with standard logic.

I realize I may not be the typical user of this board. Still, I want to use this PLL for its intended purpose - processing 1PPS signals (from a GPS, for example) and generating synchronized clocks for microprocessors. The AD9545 Evaluation Board User Guide does hint that Analog Devices had users like me in mind, so I’m not sure where things went wrong. Needing to desolder components to achieve basic functionality seems excessive - adjusting jumpers is one thing, but desoldering feels like a step too far.