Enable Quad-SPI at 62 MHz on Lattice ECP5 Evaluation Board

I wanted to confirm the speed of different configuration methods for Lattice ECP5 FPGAs by using the ECP5 Evaluation Board. The FPGA (LFE5UM5G-85F-8BG381) is used as a JTAG to SPI bridge, to program the onboard MX25L12833F SPI Flash. This complicates the flow slightly and you have to use quite a few Lattice Diamond provided tools to get the job done.

I wanted to achieve both of the following:

1. The configuration load sequence should use the 0xEB (4READ, Quad I/O Fast Read) command for reading the majority of the bitstream
2. The load should occur at a high speed, specifically 62 MHz

I have a simple design (a basic LED blinker) that loads successfully using the Slow Read command (0x03) at up to 38.8 MHz, confirming that the hardware and basic setup are functional. In order to get up to 62 MHz we can use the Fast SPI command (0x0B), which essentially adds a few dummy cycles before the first read. The steps to use Fast SPI are mostly similar to the ones I describe below. So let's focus on the main project of QSPI. This uses 4 SPI Flash pins bidirectionally.

To enable QSPI loading, these are the steps I follow:

a) In Lattice Diamond's Spreadsheet View (Global tab) I select MCCLK 62MHz and CONFIG_MODE=SPI_QUAD. This sets the following sysCONFIG preferences in the .lpf file:

SYSCONFIG MCCLK_FREQ=62 CONFIG_MODE=SPI_QUAD SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE ;

I then regenerate the bitstream (.bit file).

b) Using the Lattice Diamond Deployment Tool, I select "External Memory > Advanced SPI Flash > Quad I/O SPI Flash Read" to generate an .mcs file from the .bit file.

c) In Lattice Diamond Programmer, I configure the chain for SPI Background Programming through the ECP5's JTAG. I select "SPI Flash Erase, Program, Verify" with the device as MX25L12833F/16-pin SOP, loaded the .mcs file, and program the flash.

d) This step is important and specific to the Quad mode. To set the Quad Enable (QE) bit (bit 6 in the Status Register) to 1 on the MX25L12833F, I use the Lattice Download Debugger with a custom .svf script that issues Write Enable (0x06), Write Status Register (0x01 with value 0x40). I confirm the QE bit is set by reading the Status Register (0x05) afterward. I provide the contents of this script below.

After programming, I reboot the board (power cycle) and the device boots as expected. It takes just 60ms to configure the FPGA which is a great joy!

The .svf file is a trimmed down configuration file I opened and edited with the Lattice Download Debugger:

STATE RESET;

STATE RESET;

HDR 0 ;

HIR 0 ;

TDR 0 ;

TIR 0 ;

ENDDR IDLE;

ENDIR IDLE;

FREQUENCY 1.00E+006 HZ;

STATE IDLE;

ENDDR DRPAUSE;

ENDIR IRPAUSE;

SIR 8 TDI (FF);

STATE IDLE;

RUNTEST 32 TCK;

RUNTEST 2.00E-002 SEC;

SIR 8 TDI (3A);

SDR 16 TDI (68FE);

STATE IDLE;

RUNTEST 32 TCK;

RUNTEST 2.00E-002 SEC;

SDR 8 TDI (D5);

SDR 32 TDI (000000F9)

TDO (18FFFFFF)

MASK (FF000000);

// -------- MODIFICATIONS START HERE --------

SDR 8 TDI (60);  // WREN(0x06)

STATE DRPAUSE;

RUNTEST 2.50E-002 SEC;

// Set QE (bit 6 of status register)

SDR 16 TDI (0280);

STATE DRPAUSE;

RUNTEST 2.50E-002 SEC;

// Read Status Register

LOOP 100;

STATE DRPAUSE;

RUNTEST 2.50E-002 SEC;

SDR 16 TDI (00A0)

TDO (00FF)

MASK (8100);

ENDLOOP ;

// -------- END OF MODIFICATIONS --------

 

STATE DRPAUSE;

SIR 8 TDI (FF);

STATE IDLE;

RUNTEST 32 TCK;

RUNTEST 2.00E-002 SEC;

STATE RESET;

// ENDVME